1. Field of the Invention
The present invention relates to an integrated circuit having a testing terminal, and more particularly to a structure of an integrated circuit formed of MOS transistors and having a terminal for inputting and outputting a test signal for a performance test thereof.
2. Description of the Prior Art
A semiconductor integrated circuit containing complex functional circuits, namely, a large-scale integrated circuit (LSI) which is formed in a LSI chip, requires a large number of input and output pins for making tests of individual circuits in the LSI.
In order to decrease the number of the input and output pins for testing, an integrated circuit provided therein with a register for testing to store testing data is known and disclosed in Japanese Patent Publication No. 52-29897.
With such an integrated circuit having the testing register, while it has been possible to test one section of the integrated circuit at one time of testing, a real-time test for the entire circuit has been difficult. Further, since the integrated circuit to be tested has to be divided into sections for the sake of simplification of test sequence and identification of a trouble mode, when it becomes necessary to provide a continuous analog waveform for the integrated circuit as its own essential input and output signal, it has become difficult to synchronize the analog waveform with other digital test data to be simultaneously applied to other section, and so such a test has been impossible.